A low-power architecture for the design of a one-dimensional median filter

Ren Der Chen, Pei-Yin Chen, Chun Hsien Yeh

研究成果: Article

12 引文 斯高帕斯(Scopus)

摘要

This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced.

原文English
文章編號6951341
頁(從 - 到)266-270
頁數5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
62
發行號3
DOIs
出版狀態Published - 2015 三月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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