A low power duobinary voltage mode transmitter

Ming Hung Chien, Yen Long Lee, Jih Ren Goh, Soon Jyh Chang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.

原文English
主出版物標題ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509060238
DOIs
出版狀態Published - 2017 八月 11
事件22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan
持續時間: 2017 七月 242017 七月 26

出版系列

名字Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(列印)1533-4678

Other

Other22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
國家/地區Taiwan
城市Taipei
期間17-07-2417-07-26

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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