A low-power IP design of viterbi decoder with dynamic threshold setting

Yi Ming Lin, Wan Ching Liu, Li Yuan Chang, Chih Yuan Lien, Pei-Yin Chen, Shung Chih Chen

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

原文English
主出版物標題ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題Nano-Bio Circuit Fabrics and Systems
頁面585-588
頁數4
DOIs
出版狀態Published - 2010
事件2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
持續時間: 2010 五月 302010 六月 2

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家France
城市Paris
期間10-05-3010-06-02

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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