摘要
In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.
原文 | English |
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主出版物標題 | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems |
主出版物子標題 | Nano-Bio Circuit Fabrics and Systems |
頁面 | 585-588 |
頁數 | 4 |
DOIs | |
出版狀態 | Published - 2010 |
事件 | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France 持續時間: 2010 五月 30 → 2010 六月 2 |
Other
Other | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 |
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國家 | France |
城市 | Paris |
期間 | 10-05-30 → 10-06-02 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering