A low-power IP design of viterbi decoder with dynamic threshold setting

Yi Ming Lin; Wan Ching Liu; Li Yuan Chang; Chih Yuan Lien; Pei-Yin Chen; Shung Chih Chen

doi:10.1109/ISCAS.2010.5537527

A low-power IP design of viterbi decoder with dynamic threshold setting

Yi Ming Lin, Wan Ching Liu, Li Yuan Chang, Chih Yuan Lien, Pei-Yin Chen, Shung Chih Chen

資訊工程學系

研究成果: Conference contribution

4 引文斯高帕斯（Scopus）

摘要

In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

原文	English
主出版物標題	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題	Nano-Bio Circuit Fabrics and Systems
頁面	585-588
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537527
出版狀態	Published - 2010
事件	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France 持續時間: 2010 5月 30 → 2010 6月 2

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家/地區	France
城市	Paris
期間	10-05-30 → 10-06-02

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程

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10.1109/ISCAS.2010.5537527

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引用此

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title = "A low-power IP design of viterbi decoder with dynamic threshold setting",

abstract = "In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.",

author = "Lin, {Yi Ming} and Liu, {Wan Ching} and Chang, {Li Yuan} and Lien, {Chih Yuan} and Pei-Yin Chen and Chen, {Shung Chih}",

year = "2010",

doi = "10.1109/ISCAS.2010.5537527",

language = "English",

isbn = "9781424453085",

pages = "585--588",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

Lin, YM, Liu, WC, Chang, LY, Lien, CY, Chen, P-Y & Chen, SC 2010, A low-power IP design of viterbi decoder with dynamic threshold setting. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537527, 頁 585-588, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10-05-30. https://doi.org/10.1109/ISCAS.2010.5537527

TY - GEN

T1 - A low-power IP design of viterbi decoder with dynamic threshold setting

AU - Lin, Yi Ming

AU - Liu, Wan Ching

AU - Chang, Li Yuan

AU - Lien, Chih Yuan

AU - Chen, Pei-Yin

AU - Chen, Shung Chih

PY - 2010

Y1 - 2010

N2 - In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

AB - In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

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DO - 10.1109/ISCAS.2010.5537527

M3 - Conference contribution

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SN - 9781424453085

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EP - 588

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

A low-power IP design of viterbi decoder with dynamic threshold setting

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