A low-power LFSR architecture

Tsung Chu Huang; Kuen Jong Lee

doi:10.1109/ATS.2001.990337

A low-power LFSR architecture

Tsung Chu Huang, Kuen Jong Lee

電機工程學系

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

摘要

LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.

原文	English
文章編號	80
頁（從 - 到）	470
頁數	1
期刊	Proceedings of the Asian Test Symposium
DOIs	https://doi.org/10.1109/ATS.2001.990337
出版狀態	Published - 2001

All Science Journal Classification (ASJC) codes

電氣與電子工程

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10.1109/ATS.2001.990337

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A low-power LFSR architecture

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