A low-power LFSR architecture

Tsung Chu Huang, Kuen Jong Lee

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.

原文English
文章編號80
頁(從 - 到)470
頁數1
期刊Proceedings of the Asian Test Symposium
DOIs
出版狀態Published - 2001

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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