A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

Hui Chin Tseng, Chi Sheng Lin, Hsin Hung Ou, Bin-Da Liu

研究成果: Conference article

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

原文English
文章編號1349346
頁(從 - 到)252-256
頁數5
期刊Proceedings of the International Symposium on Low Power Electronics and Design
2004-January
發行號January
DOIs
出版狀態Published - 2004 一月 1
事件2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
持續時間: 2004 八月 92004 八月 11

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

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