A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications

Shuenn-Yuh Lee, Liang Hung Wang, Tsung Yen Chen, Chih Tao Yu

研究成果: Paper

10 引文 (Scopus)

摘要

A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

原文English
頁面1492-1495
頁數4
DOIs
出版狀態Published - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 2012 五月 202012 五月 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家Korea, Republic of
城市Seoul
期間12-05-2012-05-23

指紋

Mixer circuits
Zigbee
Low noise amplifiers
Electric power utilization
Thermal noise
Bias currents
Noise figure
Specifications
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

Lee, S-Y., Wang, L. H., Chen, T. Y., & Yu, C. T. (2012). A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. 1492-1495. 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271531
Lee, Shuenn-Yuh ; Wang, Liang Hung ; Chen, Tsung Yen ; Yu, Chih Tao. / A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.4 p.
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abstract = "A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.",
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Lee, S-Y, Wang, LH, Chen, TY & Yu, CT 2012, 'A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications' 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 12-05-20 - 12-05-23, 頁 1492-1495. https://doi.org/10.1109/ISCAS.2012.6271531

A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. / Lee, Shuenn-Yuh; Wang, Liang Hung; Chen, Tsung Yen; Yu, Chih Tao.

2012. 1492-1495 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.

研究成果: Paper

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N2 - A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

AB - A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

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Lee S-Y, Wang LH, Chen TY, Yu CT. A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. 2012. 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271531