A low power synthesis flow for multi-rate systems

Hsin Pang Kuo, Alan P. Su, Kuen-Jong Lee

研究成果: Conference contribution

摘要

In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

原文English
主出版物標題2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509039692
DOIs
出版狀態Published - 2017 六月 5
事件2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
持續時間: 2017 四月 242017 四月 27

Other

Other2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
國家Taiwan
城市Hsinchu
期間17-04-2417-04-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

指紋 深入研究「A low power synthesis flow for multi-rate systems」主題。共同形成了獨特的指紋。

  • 引用此

    Kuo, H. P., Su, A. P., & Lee, K-J. (2017). A low power synthesis flow for multi-rate systems. 於 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939677] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939677