A low-spurious low-power 12-bit 300MS/s DAC with 0.1mm2 in 0.18μm CMOS process

Wei Te Lin, Tai Haur Kuo

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

A low-spurious low-power 12-bit 300MS/s digital-to-analog converter (DAC) is proposed with only 0.1mm2 active area in a 0.18μm CMOS process. Measured performance achieves > 70dB spurious-free dynamic range (SFDR) in the whole Nyquist bandwidth and consumes 35mW. Two popular figure-of-merits (FoMs) are used to compare this design with other published DACs, with the proposed design performing best.

原文English
主出版物標題2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
出版狀態Published - 2013 十二月 23
事件2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
持續時間: 2013 六月 32013 六月 5

出版系列

名字2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
國家Hong Kong
城市Hong Kong
期間13-06-0313-06-05

    指紋

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此

Lin, W. T., & Kuo, T. H. (2013). A low-spurious low-power 12-bit 300MS/s DAC with 0.1mm2 in 0.18μm CMOS process. 於 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628035] (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013). https://doi.org/10.1109/EDSSC.2013.6628035