A low store energy and robust ReRAM-based flip-flop for normally off microprocessors

Tsai Kan Chien, Lih Yih Chiou, Yao Chun Chuang, Shyh Shyuan Sheu, Heng Yuan Li, Pei Hua Wang, Tzu Kun Ku, Ming Jinn Tsai, Chih I. Wu

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

Normally-off computing (NoC) is one of promising techniques that benefits microsystems with long sleep time. Because NoC can turn off power to achieve zero power consumption and can activate microsystems instantly. This study proposes a novel resistive random access memory (ReRAM)-based nonvolatile flip-flop (NVFF), fabricated using 90-nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. The proposed NVFF uses a complementary structure with one-phase store to mitigate limitation on store energy and was verified as the registers in three pipeline stages of a NV multiplier-and-accumulator macro. The proposed ReRAM-based NVFF, compared with the state-of-the-art complementary design, can reduce store energy by 36.4%, restore time by 64.2%, and circuit area by 42.8%. The proposed design was also superior in reducing restoration error (by 9.44%) under hardship condition compared to NVFFs with a single NV device.

原文English
主出版物標題ISCAS 2016 - IEEE International Symposium on Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2803-2806
頁數4
ISBN(電子)9781479953400
DOIs
出版狀態Published - 2016 7月 29
事件2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
持續時間: 2016 5月 222016 5月 25

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2016-July
ISSN(列印)0271-4310

Other

Other2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
國家/地區Canada
城市Montreal
期間16-05-2216-05-25

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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