A low-voltage and area-efficient adaptive SI SDADC for bio-acquisition microsystems

Chih Jen Cheng, Shuenn Yuh Lee, Yuan Lo

研究成果: Paper同行評審

摘要

An ultra-low voltage adaptive Sigma-Delta Analog-to-Digital Converter (SDADC) with a 10-bit dynamic range for biomicrosystem applications is presented. The proposed SDADC includes a Switched-current Sigma-Delta Modulator (SISDM) and a digital decimator. Moreover, a new single-multiplier structure is presented to implement the Finite Impulse Response (FIR) digital filters which are the major hardware elements in the decimator. Measurement results show that the SISDM has a dynamic range over 60dB and a power consumption of 180μW with an input signal of 1.25kHz sinusoid wave and 5kHz bandwidth under a single 0.8V power supply for ENG signals. Besides, the post layout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60dB without harming by digital circuits.

原文English
頁面431-434
頁數4
DOIs
出版狀態Published - 2006 12月 1
事件2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
持續時間: 2006 11月 132006 11月 15

Other

Other2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區China
城市Hangzhou
期間06-11-1306-11-15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電子、光磁材料

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