A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen, Chung-Ho Chen

研究成果: Conference contribution

15 引文 斯高帕斯(Scopus)

摘要

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

原文English
主出版物標題Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
頁面361-366
頁數6
出版狀態Published - 2005 十二月 1
事件2005 Intelligent Sensors, Sensor Networks and Information Processing Conference - Melbourne, Australia
持續時間: 2005 十二月 52005 十二月 8

出版系列

名字Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
2005

Other

Other2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
國家Australia
城市Melbourne
期間05-12-0505-12-08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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