A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen; Chung Ho Chen

A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen
, Chung Ho Chen

電機工程學系

研究成果: Conference contribution

16 引文斯高帕斯（Scopus）

摘要

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

原文	English
主出版物標題	Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
頁面	361-366
頁數	6
出版狀態	Published - 2005
事件	2005 Intelligent Sensors, Sensor Networks and Information Processing Conference - Melbourne, Australia 持續時間: 2005 12月 5 → 2005 12月 8

出版系列

名字	Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
卷	2005

Other

Other	2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
國家/地區	Australia
城市	Melbourne
期間	05-12-05 → 05-12-08

All Science Journal Classification (ASJC) codes

一般工程

其它文件與鏈接

引用此

Chen, C. M., & Chen, C. H. (2005). A memory efficient architecture for deblocking filter in H.264 using vertical processing order. 於 Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference (頁 361-366). 文章 1595606 (Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference; 卷 2005).

@inproceedings{6ee398556d0a4890aca799073468a719,

title = "A memory efficient architecture for deblocking filter in H.264 using vertical processing order",

abstract = "In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129\% faster than the advanced architecture of previous proposal.",

author = "Chen, \{Chung Ming\} and Chen, \{Chung Ho\}",

year = "2005",

language = "English",

isbn = "0780393996",

series = "Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference",

pages = "361--366",

booktitle = "Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference",

note = "2005 Intelligent Sensors, Sensor Networks and Information Processing Conference ; Conference date: 05-12-2005 Through 08-12-2005",

}

Chen, CM & Chen, CH 2005, A memory efficient architecture for deblocking filter in H.264 using vertical processing order. 於 Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference., 1595606, Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference, 卷 2005, 頁 361-366, 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference, Melbourne, Australia, 05-12-05.

A memory efficient architecture for deblocking filter in H.264 using vertical processing order. / Chen, Chung Ming; Chen, Chung Ho.
Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference. 2005. p. 361-366 1595606 (Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference; 卷 2005).

研究成果: Conference contribution

TY - GEN

T1 - A memory efficient architecture for deblocking filter in H.264 using vertical processing order

AU - Chen, Chung Ming

AU - Chen, Chung Ho

PY - 2005

Y1 - 2005

N2 - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

AB - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

UR - https://www.scopus.com/pages/publications/33847179855

UR - https://www.scopus.com/pages/publications/33847179855#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:33847179855

SN - 0780393996

SN - 9780780393998

T3 - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

SP - 361

EP - 366

BT - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

T2 - 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

Y2 - 5 December 2005 through 8 December 2005

ER -

A memory efficient architecture for deblocking filter in H.264 using vertical processing order

摘要

出版系列

Other

All Science Journal Classification (ASJC) codes

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引用此