A memory yield improvement scheme combining built-in self-repair and error correction codes

Tze Hsin Wu, Po Yuan Chen, Mincent Lee, Bin Yen Lin, Cheng Wen Wu, Chen Hung Tien, Hung Chih Lin, Hao Chen, Ching Nen Peng, Min Jer Wang

研究成果: Conference contribution

16 引文 斯高帕斯(Scopus)


Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this paper, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement. Many modern memories are equipped with ECC in addition to BISR. We evaluate the back-end flow that combines both ECC and BIRA to determine whether yield can be improved by proper sequencing of the two steps. We also collect and identify important failure patterns and their distributions from over 100,000 sample memory instances, which are used to enhance the EEMR scheme that incorporates ECC. As ECC is failure pattern sensitive, careful evaluation from realistic failure bitmaps is necessary. We also verify the feasibility of implementing the proposed EEMR scheme by real test data. Experimental results from industrial 4Mb memory instances show that the proposed EEMR scheme gains over 2% instance yield on average, as compared with the traditional scheme. We also investigate the reliability of the EEMR scheme with different ECC specifications and BIRA algorithms.

主出版物標題ITC 2012 - International Test Conference 2012, Proceedings
出版狀態Published - 2012 十二月 1
事件2012 International Test Conference, ITC 2012 - Anaheim, CA, United States
持續時間: 2012 十一月 62012 十一月 8


名字Proceedings - International Test Conference


Conference2012 International Test Conference, ITC 2012
國家United States
城市Anaheim, CA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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