A mesh-structured scalable IPsec processor

Mao Yin Wang, Cheng Wen Wu

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

IP security (IPsec) protocols are widely used to protect sensitive data over the Internet. For equipment linked by high-bandwidth optical fibers, the throughput requirement usually results in the adoption of high-performance network security processors. In this paper, we propose a parallel mesh-structured IPsec (MIPsec) processor, which executes the IPsec protocols for Internet security gateway applications. We have developed several area-efficient cryptographic IPs embedded in MIPsec to lower silicon cost. Thanks to structural regularity, the simple deterministic programming of MIPsec guarantees high utilization of the hardware. Also, both handshake and contention issues are solved in the scheme, such that performance can be scaled up. Specifically, the 6.23-million-gate MIPsec achieves 10-Gb/s wire speed for each routing direction. The proposed MIPsec is suitable for transport mode or other crypto mix as well.

原文English
文章編號5169966
頁(從 - 到)725-731
頁數7
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
18
發行號5
DOIs
出版狀態Published - 2010 五月 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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