A multi channel chopper modulated neural recording system

Mustafa Dagtekin, Wentai Liu, Rizwan Bashirullah

研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)


Presented herein is a fully integrated low-noise CMOS multi-channel amplifier for neural recording applications. The circuit employs the chopper modulation technique to reduce the effect of flicker noise and DC offset. A reduced area design implementation is achieved by trading off the increased noise margin performance of the chopper modulator for minimal amplifier area and analog multiplexing of the recording sites. A fully differential topology is used for the signal path to improve noise immunity. The analog amplifier exhibits 56 dB of gain with a 115 kHz bandwidth and a common mode rejection ratio (CMRR) of 80 dB. Simulation results show a total input referred noise less than 16 nV/√Hz. The system power consumption is approximately 750 μWatts. The fully integrated system was designed in ABN 1.6-um single poly n-well CMOS process.

頁(從 - 到)757-760
期刊Annual Reports of the Research Reactor Institute, Kyoto University
出版狀態Published - 2001
事件23rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society - Istanbul, Turkey
持續時間: 2001 10月 252001 10月 28

All Science Journal Classification (ASJC) codes

  • 能源工程與電力技術
  • 機械工業


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