A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique

K. Vichienchom, M. Clements, W. Liu

研究成果: Conference article同行評審

摘要

A CMOS clock and data recovery circuit for multi-gigabit data rates is described. It uses a multiphase PLL and parallel sampling techniques to reduce the speed requirements on the circuits. A parallel phase detection technique that results in linear loop control and improves loop stability is introduced. We present a new charge-pump circuit that encodes phase error into current amplitude, eliminating the problem of creating precise timing pulses to control switches. The proposed circuit was designed using TSMC 0.35 μm process parameters and verified by simulations under the presence of channel distortion and switching noise. Simulation results show that the circuit is capable of recovering clock and data at a speed of 2 Gbps.

原文English
頁(從 - 到)IV238-IV241
期刊Materials Research Society Symposium - Proceedings
626
出版狀態Published - 2001
事件Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
持續時間: 2000 4月 242000 4月 27

All Science Journal Classification (ASJC) codes

  • 一般材料科學
  • 凝聚態物理學
  • 材料力學
  • 機械工業

指紋

深入研究「A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique」主題。共同形成了獨特的指紋。

引用此