A multi-stage fault-tolerant multiplier with triple module redundancy (TMR) technique

Yuan Ho Chen, Chih Wen Lu, Shian Shing Shyu, Chung Lin Lee, Ting Chia Ou

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this study, a multistage fault-tolerant (MSFT) scheme for two fixed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-μm CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 × 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 × 64 Type-I MSFT multiplier is only 0.21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 × 64 Type-II MSFT multiplier achieves an area-delay-fault efficiency (ATF) that is 11-fold of the value of the original TMR multiplier.

原文English
文章編號1450074
期刊Journal of Circuits, Systems and Computers
23
發行號5
DOIs
出版狀態Published - 2014 6月

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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