A multi-tile reconfigurable platform design for DSP applications

Jer-Min Jou, Chien Ming Sun, Yuan Chin Wu, Ming Chao Lee, Ye Xuan Yan, Hong Yi Su, Haoi Yang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Microprocessors are increasingly supplemented with reconfigurable logic, such as field-programmable gate arrays (FPGAs), in embedded system. Because the reconfigurable architecture provide extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties and improving the integrating of IP components. Here, we presented an efficient multi-tile reconfigurable hardware platform with the coarse-grained floating-point function units for fast multimedia signal processing. We have verified the platform by an example of mapping an audio encoder on the ARM Integrator, and experimental results show that the average speedup is 3.316 compared with the software-only approach.

原文English
主出版物標題Proceedings of the Second IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing
頁面325-330
頁數6
2005
出版狀態Published - 2005
事件2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing - Novosibirsk, Russian Federation
持續時間: 2005 六月 202005 六月 24

Other

Other2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing
國家/地區Russian Federation
城市Novosibirsk
期間05-06-2005-06-24

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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