A multi-tile reconfigurable platform design for DSP applications

Jer-Min Jou; Chien Ming Sun; Yuan Chin Wu; Ming Chao Lee; Ye Xuan Yan; Hong Yi Su; Haoi Yang

A multi-tile reconfigurable platform design for DSP applications

Jer-Min Jou, Chien Ming Sun, Yuan Chin Wu, Ming Chao Lee, Ye Xuan Yan, Hong Yi Su, Haoi Yang

電機工程學系

研究成果: Conference contribution

1 引文斯高帕斯（Scopus）

摘要

Microprocessors are increasingly supplemented with reconfigurable logic, such as field-programmable gate arrays (FPGAs), in embedded system. Because the reconfigurable architecture provide extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties and improving the integrating of IP components. Here, we presented an efficient multi-tile reconfigurable hardware platform with the coarse-grained floating-point function units for fast multimedia signal processing. We have verified the platform by an example of mapping an audio encoder on the ARM Integrator, and experimental results show that the average speedup is 3.316 compared with the software-only approach.

原文	English
主出版物標題	Proceedings of the Second IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing
頁面	325-330
頁數	6
卷	2005
出版狀態	Published - 2005
事件	2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing - Novosibirsk, Russian Federation 持續時間: 2005 6月 20 → 2005 6月 24

Other

Other	2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing
國家/地區	Russian Federation
城市	Novosibirsk
期間	05-06-20 → 05-06-24

All Science Journal Classification (ASJC) codes

工程 (全部)

其它文件與鏈接

引用此

@inproceedings{4238d07bca734ab986ac37efce593eef,

title = "A multi-tile reconfigurable platform design for DSP applications",

abstract = "Microprocessors are increasingly supplemented with reconfigurable logic, such as field-programmable gate arrays (FPGAs), in embedded system. Because the reconfigurable architecture provide extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties and improving the integrating of IP components. Here, we presented an efficient multi-tile reconfigurable hardware platform with the coarse-grained floating-point function units for fast multimedia signal processing. We have verified the platform by an example of mapping an audio encoder on the ARM Integrator, and experimental results show that the average speedup is 3.316 compared with the software-only approach.",

author = "Jer-Min Jou and Sun, {Chien Ming} and Wu, {Yuan Chin} and Lee, {Ming Chao} and Yan, {Ye Xuan} and Su, {Hong Yi} and Haoi Yang",

year = "2005",

language = "English",

isbn = "0889864772",

volume = "2005",

pages = "325--330",

booktitle = "Proceedings of the Second IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing",

note = "2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing ; Conference date: 20-06-2005 Through 24-06-2005",

}

Jou, J-M, Sun, CM, Wu, YC, Lee, MC, Yan, YX, Su, HY & Yang, H 2005, A multi-tile reconfigurable platform design for DSP applications. 於 Proceedings of the Second IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing. 卷 2005, 頁 325-330, 2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing, Novosibirsk, Russian Federation, 05-06-20.

TY - GEN

T1 - A multi-tile reconfigurable platform design for DSP applications

AU - Jou, Jer-Min

AU - Sun, Chien Ming

AU - Wu, Yuan Chin

AU - Lee, Ming Chao

AU - Yan, Ye Xuan

AU - Su, Hong Yi

AU - Yang, Haoi

PY - 2005

Y1 - 2005

N2 - Microprocessors are increasingly supplemented with reconfigurable logic, such as field-programmable gate arrays (FPGAs), in embedded system. Because the reconfigurable architecture provide extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties and improving the integrating of IP components. Here, we presented an efficient multi-tile reconfigurable hardware platform with the coarse-grained floating-point function units for fast multimedia signal processing. We have verified the platform by an example of mapping an audio encoder on the ARM Integrator, and experimental results show that the average speedup is 3.316 compared with the software-only approach.

AB - Microprocessors are increasingly supplemented with reconfigurable logic, such as field-programmable gate arrays (FPGAs), in embedded system. Because the reconfigurable architecture provide extremely advantages such as reducing the cost, time and complexity of design, and diminishing the difficulties and improving the integrating of IP components. Here, we presented an efficient multi-tile reconfigurable hardware platform with the coarse-grained floating-point function units for fast multimedia signal processing. We have verified the platform by an example of mapping an audio encoder on the ARM Integrator, and experimental results show that the average speedup is 3.316 compared with the software-only approach.

UR - http://www.scopus.com/inward/record.url?scp=33751276921&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33751276921&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33751276921

SN - 0889864772

SN - 9780889864771

VL - 2005

SP - 325

EP - 330

BT - Proceedings of the Second IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing

T2 - 2nd IASTED International Multi-Conference on Automation, Control, and Information Technology - Signal and Image Processing

Y2 - 20 June 2005 through 24 June 2005

ER -

A multi-tile reconfigurable platform design for DSP applications

摘要

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All Science Journal Classification (ASJC) codes

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