A new design to prevent fault equivalence in PLA's

B. D. Liu, G. T. Shaw

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

The fault equivalence problem in programmable logic arrays (PLAs) is introduced. Some design rules are proposed. Based on the pseudoexhaustive testable PLA structure, a diagnosis algorithm was developed and implemented on a SUN 3/110 workstation in C language. Experimental results show that this design and the algorithm are quite efficient for PLA fault diagnosis.

原文English
頁(從 - 到)2752-2755
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 1990 12月 1
事件1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
持續時間: 1990 5月 11990 5月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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