A new isolation technology for mixed-mode and general mixed-technology SOC chips

C. P. Liao, K. C. Juang, T. H. Huang, D. S. Duh, T. T. Yang, M. N. Liu

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)


With higher levels of integration in VLSI, the importance of limiting undesirable interactions (i.e. crosstalk) between different circuits fabricated on a common Si substrate is increasing. Such interaction, known as substrate coupling, is more significant in mixed-mode or mixed-technology ICs, particularly in the high frequency regime. In commercial operations, the procedure for mixed-mode (or mixed-technology) device development has always become a laborious cycle of circuit design/simulation, layout, pilot run, and testing, before a final compromised (not necessarily optimized) result is reached. Consequently, the whole process of mixed-technology IC production is very time-consuming, costly and may lead to poor market timing. In this paper, a new isolation method is proposed in which penetrating protons are applied at selected locations on each IC prior to packaging. Experimental results indicated that a 25-30 dB improvement could be achieved by applying a low-fluence proton bombardment to the isolation-intended region of a metal pad pattern on a ∼10 Ω-cm Si substrate. In addition, a proton-enhanced alternative-SOI structure from initially lightly doped wafers may be achieved for all SOC (system-on-a-chip) purposes. This option fully exploits the proton treatment, since the resistivity enhancement is most effective in lightly doped silicon. This proton isolation technology should be of interest to any mixed-technology SOC producer longing for the opportunity to break the aforementioned development cycle from the outset into a more familiar development sequence, while still leading to as-designed, optimum products.

主出版物標題2000 Semiconductor Manufacturing Technology Workshop
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)0780363744, 9780780363748
出版狀態Published - 2000 一月 1
事件Semiconductor Manufacturing Technology Workshop - Hsinchu, Taiwan
持續時間: 2000 六月 142000 六月 15


名字2000 Semiconductor Manufacturing Technology Workshop


OtherSemiconductor Manufacturing Technology Workshop

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Electronic, Optical and Magnetic Materials

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    Liao, C. P., Juang, K. C., Huang, T. H., Duh, D. S., Yang, T. T., & Liu, M. N. (2000). A new isolation technology for mixed-mode and general mixed-technology SOC chips. 於 2000 Semiconductor Manufacturing Technology Workshop (頁 124-132). [883093] (2000 Semiconductor Manufacturing Technology Workshop). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMTW.2000.883093