A new LFSR reseeding scheme via internal response feedback

Wei Cheng Lien, Kuen-Jong Lee, Tong Yu Hsieh, Krishnendu Chakrabarty

研究成果: Conference article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Reseeding techniques have been adopted in BIST to enhance fault detectability and shorten test application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need large storage space to store all required seeds. In this paper, we propose a new LFSR reseeding technique that employs the internal net responses of the circuit itself as the control signals to change the states of the LFSR. A novel test architecture containing a net selection logic module and an LFSR with some inversion logic is presented that can generate all required seeds on-chip in real time without any external or internal storage requirement. Experimental results on ISCAS benchmark circuits show that the presented technique can achieve 100% stuck-at fault coverage in a short test time by using only 0.23-2.36% of internal nets for reseeding control.

原文English
文章編號6690622
頁(從 - 到)97-102
頁數6
期刊Proceedings of the Asian Test Symposium
DOIs
出版狀態Published - 2013 一月 1
事件2013 22nd Asian Test Symposium, ATS 2013 - Yilan, Taiwan
持續時間: 2013 十一月 182013 十一月 21

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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