A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate

Te Kuang Chiang, Chen Chih Yo, Hong Wun Gao, Yeong Her Wang

研究成果: Conference contribution

摘要

Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

原文English
主出版物標題2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509024391
DOIs
出版狀態Published - 2016 八月 12
事件5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
持續時間: 2016 五月 42016 五月 6

出版系列

名字2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
國家Taiwan
城市Hsinchu
期間16-05-0416-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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