TY - JOUR
T1 - A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter
AU - Jacob, Vinod Kurian
AU - Yang, Jiyue
AU - He, Haoran
AU - Gupta, Puneet
AU - Wang, Kang L.
AU - Pamarti, Sudhakar
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2023/6/1
Y1 - 2023/6/1
N2 - Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is far lower than their static random access memory (SRAM)-CIM counterparts due to low device ON/ OFF ratio. In this work, we combine a nonvolatile memory based on a voltage-controlled magnetic tunneling junction (VC-MTJ) device, called voltage-controlled MRAM or VC-MRAM, and accurate switched-capacitor-based CIM using a novel in situ magnetic-to-digital converter (MDC). The VC-MTJ device has demonstrated 10× lower write energy and switching time compared to STT-MRAM device and has comparable density, read energy, and read latency. The in situ MDCs embedded inside each VC-MRAM row convert magnetically stored weight information to CMOS logic levels and enable switched-capacitor-based multiply-accumulate (MAC) operation with accuracy comparable to the state-of-the-art SRAM-CIM. This article describes the schematic and layout level design of a VC-MRAM CIM macro in 28 nm. This is the first nonvolatile CIM design to enable analog MAC computation with 256 parallel rows turned ON simultaneously without degradation in dynamic range (< 1 LSB). Detailed circuit simulations including experimentally validated VC-MTJ compact models show 1.5× higher energy efficiency and 2× higher density compared to the state-of-the-art SRAM-based CIM.
AB - Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is far lower than their static random access memory (SRAM)-CIM counterparts due to low device ON/ OFF ratio. In this work, we combine a nonvolatile memory based on a voltage-controlled magnetic tunneling junction (VC-MTJ) device, called voltage-controlled MRAM or VC-MRAM, and accurate switched-capacitor-based CIM using a novel in situ magnetic-to-digital converter (MDC). The VC-MTJ device has demonstrated 10× lower write energy and switching time compared to STT-MRAM device and has comparable density, read energy, and read latency. The in situ MDCs embedded inside each VC-MRAM row convert magnetically stored weight information to CMOS logic levels and enable switched-capacitor-based multiply-accumulate (MAC) operation with accuracy comparable to the state-of-the-art SRAM-CIM. This article describes the schematic and layout level design of a VC-MRAM CIM macro in 28 nm. This is the first nonvolatile CIM design to enable analog MAC computation with 256 parallel rows turned ON simultaneously without degradation in dynamic range (< 1 LSB). Detailed circuit simulations including experimentally validated VC-MTJ compact models show 1.5× higher energy efficiency and 2× higher density compared to the state-of-the-art SRAM-based CIM.
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U2 - 10.1109/JXCDC.2023.3258431
DO - 10.1109/JXCDC.2023.3258431
M3 - Article
AN - SCOPUS:85151510405
SN - 2329-9231
VL - 9
SP - 56
EP - 64
JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
IS - 1
ER -