A novel clock-pulse-width calibration technique for charge redistribution DACs

Hugo Cruz, Hong Yi Huang, Ching Hsing Luo, Lih Yih Chiou, Shuenn Yuh Lee

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.

原文English
主出版物標題IEEE International Symposium on Circuits and Systems
主出版物子標題From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467368520
DOIs
出版狀態Published - 2017 9月 25
事件50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
持續時間: 2017 5月 282017 5月 31

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
國家/地區United States
城市Baltimore
期間17-05-2817-05-31

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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