TY - GEN
T1 - A novel clock-pulse-width calibration technique for charge redistribution DACs
AU - Cruz, Hugo
AU - Huang, Hong Yi
AU - Luo, Ching Hsing
AU - Chiou, Lih Yih
AU - Lee, Shuenn Yuh
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.
AB - This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.
UR - https://www.scopus.com/pages/publications/85032680436
UR - https://www.scopus.com/pages/publications/85032680436#tab=citedBy
U2 - 10.1109/ISCAS.2017.8050483
DO - 10.1109/ISCAS.2017.8050483
M3 - Conference contribution
AN - SCOPUS:85032680436
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -