摘要
In order to reduce the computational complexity of convolutional neural networks (CNNs), the local binary convolutional neural network (LBCNN) has been proposed. In the LBCNN, a convolutional layer is divided into two sublayers. Sublayer 1 is a sparse ternary-weighted convolutional layer, and Sublayer 2 is a 1 1 convolutional layer. With the use of two sublayers, the LBCNN has lower computational complexity and uses less memory than the CNN. In this brief, we propose a platform that includes a weight preprocessor and layer accelerator for the LBCNN. The proposed weight preprocessor takes advantage of the sparsity in the LBCNN and encodes the weight offline. The layer accelerator effectively uses the encoded data to reduce computational complexity and memory accesses for an inference. When compared to the state-of-the-art design, the experimental results show that the number of clock cycles are reduced by 76.32%, and memory usage is reduced by 39.41%. The synthesized results show that the clock period is reduced by 4.76%; the cell area is reduced by 46.48%, and the power consumption is reduced by 40.87%. The inference accuracy is the same as that of the state-of-the-art design.
| 原文 | English |
|---|---|
| 文章編號 | 9249011 |
| 頁(從 - 到) | 1413-1417 |
| 頁數 | 5 |
| 期刊 | IEEE Transactions on Circuits and Systems II: Express Briefs |
| 卷 | 68 |
| 發行號 | 4 |
| DOIs | |
| 出版狀態 | Published - 2021 4月 |
All Science Journal Classification (ASJC) codes
- 電氣與電子工程
指紋
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