A novel ESD device structure with fully silicide process for mixed high/low voltage operation

Jian Hsing Lee, J. R. Shih, Dao Hong Yang, Jone F. Chen, Kenneth Wu

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

原文English
主出版物標題2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs
出版狀態Published - 2008 9月 23
事件2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
持續時間: 2008 7月 72008 7月 11

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
國家/地區Singapore
城市Singapore
期間08-07-0708-07-11

All Science Journal Classification (ASJC) codes

  • 一般工程

指紋

深入研究「A novel ESD device structure with fully silicide process for mixed high/low voltage operation」主題。共同形成了獨特的指紋。

引用此