A novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates

Tc Kuang Chiang, Chen Chih Yo, Hong Wun Gao, Yeong Her Wang

研究成果: Conference contribution

摘要

In this paper, we present a novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of noise margin for SRG MOSFET operating in low-voltage condition is revealed. It is shown that the device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, short channel length Lg, and low supply voltage Vdd can severely degrade the noise margin NM. On the contrary, the small subthreshold slope induced by device parameters can suppress the NM degradation efficiently. Being similar to DIBL, NM degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory.

原文English
主出版物標題7th IEEE International Nanoelectronics Conference 2016, INEC 2016
發行者IEEE Computer Society
ISBN(電子)9781467389693
DOIs
出版狀態Published - 2016 十月 12
事件7th IEEE International Nanoelectronics Conference, INEC 2016 - Chengdu, China
持續時間: 2016 五月 92016 五月 11

出版系列

名字Proceedings - International NanoElectronics Conference, INEC
2016-October
ISSN(列印)2159-3523

Other

Other7th IEEE International Nanoelectronics Conference, INEC 2016
國家China
城市Chengdu
期間16-05-0916-05-11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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