This paper presents an unique offset current cancellation technique called 'multiple-path feedback compensation (MPFC)' which can greatly reduce offset currents at the output and internal nodes of SI circuits and systems. A 5th-order Chebyshev SI filter is used as an example for the implementation and the verification of the proposed MPFC technique. 90 test chips have been fabricated with a 1 μm CMOS n-well digital process. Increased percentages of the chip area and the power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signal-to-noise ratio(SNR) is increased by 3dB and the total harmonic distortion(THD) is reduced by 10dB.
|頁（從 - 到）||417-420|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1996 五月|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials