A novel test generation method for small-delay defects with user-defined fault model

Chao Jun Shang, Cheng Hung Wu, Kuen-Jong Lee, Yu Hsiang Chen

研究成果: Conference contribution

摘要

To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.

原文English
主出版物標題2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728106557
DOIs
出版狀態Published - 2019 四月 1
事件2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
持續時間: 2019 四月 222019 四月 25

出版系列

名字2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
國家Taiwan
城市Hsinchu
期間19-04-2219-04-25

指紋

Defects
defects
stems
time measurement
Networks (circuits)
very large scale integration
industries
chips
Industry

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation
  • Computer Networks and Communications
  • Hardware and Architecture

引用此文

Shang, C. J., Wu, C. H., Lee, K-J., & Chen, Y. H. (2019). A novel test generation method for small-delay defects with user-defined fault model. 於 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741773] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741773
Shang, Chao Jun ; Wu, Cheng Hung ; Lee, Kuen-Jong ; Chen, Yu Hsiang. / A novel test generation method for small-delay defects with user-defined fault model. 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).
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abstract = "To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2{\%} pattern count and increase 0.74{\%} DTC on average for ISCAS89 and IWLS05 benchmark circuits.",
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Shang, CJ, Wu, CH, Lee, K-J & Chen, YH 2019, A novel test generation method for small-delay defects with user-defined fault model. 於 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741773, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 19-04-22. https://doi.org/10.1109/VLSI-DAT.2019.8741773

A novel test generation method for small-delay defects with user-defined fault model. / Shang, Chao Jun; Wu, Cheng Hung; Lee, Kuen-Jong; Chen, Yu Hsiang.

2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741773 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

研究成果: Conference contribution

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Shang CJ, Wu CH, Lee K-J, Chen YH. A novel test generation method for small-delay defects with user-defined fault model. 於 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). https://doi.org/10.1109/VLSI-DAT.2019.8741773