A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

Jau Yi Wu, Hwei Heng Wang, Po Wen Sze, Yeong-Her Wang, Mau-phon Houng

研究成果: Letter

9 引文 (Scopus)

摘要

A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

原文English
頁(從 - 到)237-239
頁數3
期刊IEEE Electron Device Letters
23
發行號5
DOIs
出版狀態Published - 2002 五月 1

指紋

Fabrication
Oxidation
Liquids
gallium arsenide
Costs
Temperature

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

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T1 - A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

AU - Wu, Jau Yi

AU - Wang, Hwei Heng

AU - Sze, Po Wen

AU - Wang, Yeong-Her

AU - Houng, Mau-phon

PY - 2002/5/1

Y1 - 2002/5/1

N2 - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

AB - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

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