A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

Lih Yih Chiou, Chi Ray Huang, Ming Hung Wu

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

Adaptive design is one of the most promising approaches for mitigating the large design margin used by dynamically scaling the supply voltage and frequency of integrated circuits. A low cost and power efficient variation detection circuit is one of the critical components intended to achieve the goal of adaptive control. In this paper, we proposed a pulse-based timing error prediction mechanism that can minimize safety margins with low design overhead. When compared with the conventional canary-based circuit technique, 28.7% power reduction is achieved under 50% data activity. Moreover, an average of 48.3% power reduction is obtained across different process corners at ultra-low voltage regime as compared to the worst case design.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1215-1218
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 2014
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 2014 6月 12014 6月 5

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家/地區Australia
城市Melbourne, VIC
期間14-06-0114-06-05

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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