A power-efficient sizing methodology of SAR ADCs

Chun Po Huang, Soon Jyh Chang, Guan Ying Huang, Cheng Wu Lin

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

Analog-to-digital converter (ADC) is a vital component for modern electronic systems, but designing an ADC usually takes much time and effort. Though several synthesis methods have been presented for analog circuits, there exists limited works focusing on ADC design automation. In this paper, we propose a systematic sizing methodology to minimize the power consumption for successive approximation register (SAR) ADCs in transistor level. This method manipulates the characteristics of SAR ADC to develop an efficient searching algorithm for shortening the sizing time. The time complexity of our method is O(2 log 2 S), where jSj is the number of candidates in the searching space. According to the proposed sizing flow, we develop a sizing tool which is independent of manufacturing process and is able to minimize power consumption for SAR ADCs. By using the developed sizing tool, a proof-of-concept prototype was carried out within only 15 minutes and fabricated in a 1P4M 0.11μm process. The measurement results show the prototype demonstrates a high competitiveness compared to other state-of-the-art works on performance and power efficiency.

原文English
頁面365-368
頁數4
DOIs
出版狀態Published - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 2012 五月 202012 五月 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區Korea, Republic of
城市Seoul
期間12-05-2012-05-23

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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