A feasible device design methodology for bulk FinFETs is proposed. An optimal yet simple process technique is shown to achieve good performance while maintaining low leakage current with thin gate-to-substrate isolation oxide and moderately doped substrate. In contrast, high substrate doping underneath the fin and thick isolation oxide are usually needed to prevent substrate leakage in conventional bulk FinFETs. A design window accounting for isolation oxide thickness and substrate doping level is proposed for low power and high performance application. Sufficient substrate doping (in the mid-1018 cm-3 range) and proper isolation oxide of 10s nm are suggested based on our performance projection.
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