A processor-based built-in self-repair design for embedded memories

Chin Lung Su, Rei Fu Huang, Cheng Wen Wu

研究成果: Conference contribution

29 引文 斯高帕斯(Scopus)

摘要

We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost every system-on-chip (SOC) product, in addition to many distinct features. By reusing the embedded processor, the controller and redundancy analysis circuit of a typical BISR design can be removed. Also, the test algorithm and redundancy analysis/allocation algorithm are easily programmable, greatly increasing the design flexibility. We also have developed a memory wrapper that allows at-speed testing of the memory cores. The area overhead of the proposed BISR scheme is low, since only the memory wrapper needs to be realized explicitly. Our experiments show that the BISR area overhead for a typical 8Kx32 SRAM is lower than 1%.

原文English
主出版物標題Proceedings - 12th Asian Test Symposium, ATS 2003
發行者IEEE Computer Society
頁面366-371
頁數6
ISBN(電子)0769519512
DOIs
出版狀態Published - 2003 一月 1
事件12th Asian Test Symposium, ATS 2003 - Xi'an, China
持續時間: 2003 十一月 162003 十一月 19

出版系列

名字Proceedings of the Asian Test Symposium
2003-January
ISSN(列印)1081-7735

Other

Other12th Asian Test Symposium, ATS 2003
國家China
城市Xi'an
期間03-11-1603-11-19

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此

Su, C. L., Huang, R. F., & Wu, C. W. (2003). A processor-based built-in self-repair design for embedded memories. 於 Proceedings - 12th Asian Test Symposium, ATS 2003 (頁 366-371). [1250838] (Proceedings of the Asian Test Symposium; 卷 2003-January). IEEE Computer Society. https://doi.org/10.1109/ATS.2003.1250838