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A radix-2/3/22/23 MDC architecture for variable-length FFT processors

研究成果: Conference contribution

1   連結會在新分頁中開啟 引文 斯高帕斯(Scopus)

摘要

A radix-2/3/22/23 multi-path delay commutator (MDC) architecture for pipelined shared-memory fast Fourier transform (FFT) processors is proposed. By using an effective memory addressing scheme, the original processing and control characteristics of the 2m-point FFT processor are retained when processing 3·2m-point FFT, where m is an integer. The proposed variable-length FFT processor can thus be implemented more efficiently.

原文English
主出版物標題2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面180-181
頁數2
ISBN(電子)9781479987443
DOIs
出版狀態Published - 2015 8月 20
事件2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, Taiwan
持續時間: 2015 6月 62015 6月 8

出版系列

名字2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Other

Other2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
國家/地區Taiwan
城市Taipei
期間15-06-0615-06-08

All Science Journal Classification (ASJC) codes

  • 人工智慧
  • 電腦網路與通信
  • 電氣與電子工程
  • 儀器
  • 媒體技術

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