A reconfigurable architecture for entropy decoding and IDCT in H.264

Chia Cheng Lo, Shang Ta Tsai, Ming Der Shieh

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

Reconfigurable hardware is an effective design option to cope with the increasing demands of simultaneous flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), defined in the H.264 standard using the coarse-grain reconfigurable architecture. Coarse-grain reconfigurable architectures can provide obvious advantages over their fine-grain counterparts for some specific applications. By analyzing the similarities and differences between these two decoding processes, we show how to effectively merge CAVLC into a CABAC decoder. Experimental results reveal that about 1.5K savings in gate counts can be obtained using the proposed reconfigurable cell (RC) architecture, which corresponds to 25.4% area savings in implementing the CAVLC decoder. Moreover, using the idle time in RC arrays, the base cell can be extended to carry out the inverse discrete cosine transform with very limited overhead. Our entropy decoder design, operated in 66 MHz, can decode video sequences at MP@ Level 3.0 under the real-time constraint.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面279-282
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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