A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si 1-x O 2 Gate dielectric and improved electrical and hysteresis performance

Chien Hsiung Hung, Shui-Jinn Wang, Pang Yi Liu, Chien Hung Wu, Nai Sheng Wu, Hao Ping Yan, Tseng Hsing Lin

研究成果: Article

2 引文 斯高帕斯(Scopus)

摘要

The use of co-sputtered zirconium silicon oxide (Zr x Si 1-x O 2 ) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150W and with that of the ZrO2 target kept at 100W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si 1-x O 2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103mV/dec) and field effect mobility (33.76 cm2V%1 s%1).

原文English
文章編號04CG06
期刊Japanese Journal of Applied Physics
56
發行號4
DOIs
出版狀態Published - 2017 四月 1

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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