摘要
A scalable high-precision maximum/minimum circuit is designed. This circuit can be easily configured as maximum or minimum function by an enable signal without modifying the circuit structure and pre-processing input variables. The response time of the circuit is increased linearly with respect to the number of input variables. This circuit has been simulated using 0.5 μm CMOS technology by HSPICE. The results show that a cell can be a winner/loser if its input voltage is larger or smaller than those of other cells by 3 mV.
| 原文 | English |
|---|---|
| 主出版物標題 | AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs |
| 發行者 | Institute of Electrical and Electronics Engineers Inc. |
| 頁面 | 206-209 |
| 頁數 | 4 |
| ISBN（列印） | 0780357051, 9780780357051 |
| DOIs | |
| 出版狀態 | Published - 1999 一月 1 |
| 事件 | 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of 持續時間: 1999 八月 23 → 1999 八月 25 |
出版系列
| 名字 | AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs |
|---|
Other
| Other | 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 |
|---|---|
| 國家 | Korea, Republic of |
| 城市 | Seoul |
| 期間 | 99-08-23 → 99-08-25 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Electronic, Optical and Magnetic Materials
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引用此
Hung, Y. C., & Liu, B. D. (1999). A scalable high-precision CMOS max/min circuit using single comparator. 於 AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (頁 206-209). [824064] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824064