A scalable sorting architecture based on maskable WTA/MAX circuit

Shin Hong Ou, Chi Sheng Lin, Bin-Da Liu

研究成果: Conference article

8 引文 (Scopus)

摘要

Sorting plays an important role in data and digital signal/image processing. Data become easier to handle with after they are sorted. In this paper we propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort arbitrary N items of data with simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, proposed sorting system can be expanded easily by simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. Modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of proposed sorter can be easily augmented to 16-bit or 32-bit. Our sorter chip has been manufactured by TSMC 0.35μm 1P4M process with 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 2002 一月 1
事件2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
持續時間: 2002 五月 262002 五月 29

指紋

Sorting
Networks (circuits)
Image processing
Hardware
Data storage equipment
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

@article{534b4d823f8d44c9bd8f27520f115352,
title = "A scalable sorting architecture based on maskable WTA/MAX circuit",
abstract = "Sorting plays an important role in data and digital signal/image processing. Data become easier to handle with after they are sorted. In this paper we propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort arbitrary N items of data with simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, proposed sorting system can be expanded easily by simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. Modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of proposed sorter can be easily augmented to 16-bit or 32-bit. Our sorter chip has been manufactured by TSMC 0.35μm 1P4M process with 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.",
author = "Ou, {Shin Hong} and Lin, {Chi Sheng} and Bin-Da Liu",
year = "2002",
month = "1",
day = "1",
language = "English",
volume = "4",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

A scalable sorting architecture based on maskable WTA/MAX circuit. / Ou, Shin Hong; Lin, Chi Sheng; Liu, Bin-Da.

於: Proceedings - IEEE International Symposium on Circuits and Systems, 卷 4, 01.01.2002.

研究成果: Conference article

TY - JOUR

T1 - A scalable sorting architecture based on maskable WTA/MAX circuit

AU - Ou, Shin Hong

AU - Lin, Chi Sheng

AU - Liu, Bin-Da

PY - 2002/1/1

Y1 - 2002/1/1

N2 - Sorting plays an important role in data and digital signal/image processing. Data become easier to handle with after they are sorted. In this paper we propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort arbitrary N items of data with simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, proposed sorting system can be expanded easily by simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. Modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of proposed sorter can be easily augmented to 16-bit or 32-bit. Our sorter chip has been manufactured by TSMC 0.35μm 1P4M process with 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

AB - Sorting plays an important role in data and digital signal/image processing. Data become easier to handle with after they are sorted. In this paper we propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort arbitrary N items of data with simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, proposed sorting system can be expanded easily by simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. Modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of proposed sorter can be easily augmented to 16-bit or 32-bit. Our sorter chip has been manufactured by TSMC 0.35μm 1P4M process with 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=0036292991&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036292991&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0036292991

VL - 4

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -