A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Rei Fu Huang, Jin Fu Li, Jen Chieh Yeh, Cheng Wen Wu

研究成果: Conference contribution

40 引文 斯高帕斯(Scopus)

摘要

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.

原文English
主出版物標題Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002
編輯Thomas Wik, Bernard Courtois, Yervant Zorian
發行者IEEE Computer Society
頁面68-73
頁數6
ISBN(電子)0769516173
DOIs
出版狀態Published - 2002 一月 1
事件IEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002 - Isle of Bendor, France
持續時間: 2002 七月 102002 七月 12

出版系列

名字Records of the IEEE International Workshop on Memory Technology, Design and Testing
2002-January
ISSN(列印)1087-4852

Conference

ConferenceIEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002
國家/地區France
城市Isle of Bendor
期間02-07-1002-07-12

All Science Journal Classification (ASJC) codes

  • 媒體技術

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