A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Rei Fu Huang, Jin Fu Li, Jen Chieh Yeh, Cheng Wen Wu

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order improving the accuracy of the analysis results.

原文English
主出版物標題Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002
發行者Institute of Electrical and Electronics Engineers Inc.
頁面262-267
頁數6
ISBN(電子)0769516416, 9780769516417
DOIs
出版狀態Published - 2002 一月 1
事件8th IEEE International On-Line Testing Workshop, IOLTW 2002 - Isle of Bendor, France
持續時間: 2002 七月 82002 七月 10

出版系列

名字Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Conference

Conference8th IEEE International On-Line Testing Workshop, IOLTW 2002
國家/地區France
城市Isle of Bendor
期間02-07-0802-07-10

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程
  • 建模與模擬
  • 理論電腦科學

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