A software-based test methodology for direct-mapped data cache

Yi Cheng Lin, Yi Ying Tsai, Kuen Jong Lee, Cheng Wei Yen, Chung Ho Chen

研究成果: Conference contribution

14 引文 斯高帕斯(Scopus)

摘要

We present a software-based test methodology that utilizes an on-chip processor to perform test procedures for direct-mapped data cache. The cache system under test is divided into two major groups, namely the memory modules and the logic modules. For the memory modules which include the tag memory, the data memory, and the physical address tag memory, systematic procedures to transform a widely-used March algorithm into various executable instruction sequences are developed. For the logic modules, extensive analysis on the functions as well as the structures (architecture, RTL, and gate-level) of these modules is carried out and effective test instruction sequences based on the analysis are derived. A 100% fault coverage for six conventional RAM fault models and 99.13% test efficiency for single stuck-at fault model are obtained on a real 32-bit RISC processor. These results validate the viability and effectiveness of the proposed methodology for data-cache testing.

原文English
主出版物標題Proceedings of the 17th Asian Test Symposium, ATS 2008
頁面363-368
頁數6
DOIs
出版狀態Published - 2008
事件17th Asian Test Symposium, ATS 2008 - Sapporo, Japan
持續時間: 2008 十一月 242008 十一月 27

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Other

Other17th Asian Test Symposium, ATS 2008
國家/地區Japan
城市Sapporo
期間08-11-2408-11-27

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「A software-based test methodology for direct-mapped data cache」主題。共同形成了獨特的指紋。

引用此