A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator

Shuenn Yuh Lee, Chih Jen Cheng

研究成果: Paper

摘要

A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. hi addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.

原文English
頁面41-44
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

指紋

Modulators
Switches
Demodulators
FIR filters
Electric power utilization
Sampling
Hardware
Bandwidth
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Lee, S. Y., & Cheng, C. J. (2004). A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator. 41-44. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Lee, Shuenn Yuh ; Cheng, Chih Jen. / A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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abstract = "A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. hi addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.",
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Lee, SY & Cheng, CJ 2004, 'A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator', 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 頁 41-44.

A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator. / Lee, Shuenn Yuh; Cheng, Chih Jen.

2004. 41-44 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper

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N2 - A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. hi addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.

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Lee SY, Cheng CJ. A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator. 2004. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.