A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Shien Chun Luo, Lih Yih Chiou

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

原文English
文章編號5471175
頁(從 - 到)440-445
頁數6
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
57
發行號6
DOIs
出版狀態Published - 2010 6月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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