A subthreshold SRAM cell with autonomous bitline-voltage clamping

Shien Chun Luo, Lih Yih Chiou

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Ultra-low power SRAM is a promising memory for the next-generation electronics that focus on green and power-aware computing. Unfortunately, ultra-low power SRAM encounters serious timing uncertainty. One of the major problems is that the conventional voltage-clamping circuits cannot work when the bitlines have serious with-in-die variations. The full swing, usually required on the bitline, causes unwanted power dispassion. Therefore, this work proposes a novel SRAM cell that can clamp the bitline voltage autonomously. This voltage clamping is also independent in each bitline and is adapted automatically under dynamic voltage scaling. The dynamic power on bitline discharge can be saved by 75% by using the proposed structure, with an acceptable overhead in access time.

原文English
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面150-153
頁數4
DOIs
出版狀態Published - 2010 12月 1
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
持續時間: 2010 11月 182010 11月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家/地區Taiwan
城市Kaohsiung
期間10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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