A successive approximation ADC with resistor-capacitor hybrid structure

This paper presents a 10-bit 50MS/s successive approximation register (SAR) ADC with low input capacitance that uses an on-chip resistive ladder to arrange a new switching scheme. The proposed arrangement not only reduces the total input capacitance, but also performs the predictive capacitor switching sequence to further reduce the power consumption. Therefore, the proposed SAR ADC has the features of small area and low power consumption. Compared to conventional SAR ADCs, the proposed ADC reduces the input capacitance to 512 fF for 10-bit resolution. This work is fabricated in TSMC 90-nm 1P9M CMOS process. This prototype chip consumes 0.703 mW from a 1.2-V supply and the ENOB is 9.3 bits at 50 MS/s sampling rate. The resultant FoM is 28 fJ/conversion-step.