A technique for high-speed, fine-resolution pattern generation and its CMOS implementation

G. C. Moyer, M. Clements, Wentai Liu, T. Schaffer, R. K. Cavin

研究成果: Paper同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution than traditional methods and, in addition, generates high data rate patterns without the need of a high-speed clock. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 μm CMOS technology. This implementation used biased delay elements to internally compensate for temperature and process variations. Simulations indicate the implementation described in this paper can generate data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps.

原文English
頁面131-145
頁數15
DOIs
出版狀態Published - 1995
事件16th Conference on Advanced Research in VLSI, ARVLSI 1995 - Chapel Hil, United States
持續時間: 1995 3月 271995 3月 29

Conference

Conference16th Conference on Advanced Research in VLSI, ARVLSI 1995
國家/地區United States
城市Chapel Hil
期間95-03-2795-03-29

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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