A test integration methodology for 3D integrated circuits

Che Wei Chou, Jin Fu Li, Ji Jan Chen, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

研究成果: Conference contribution

28 引文 斯高帕斯(Scopus)

摘要

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.

原文English
主出版物標題Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
頁面377-382
頁數6
DOIs
出版狀態Published - 2010 十二月 1
事件2010 19th IEEE Asian Test Symposium, ATS 2010 - Shanghai, China
持續時間: 2010 十二月 12010 十二月 4

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Other

Other2010 19th IEEE Asian Test Symposium, ATS 2010
國家/地區China
城市Shanghai
期間10-12-0110-12-04

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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