A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Chung Min Shiao, Wei Cheng Lien, Kuen-Jong Lee

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

Test-per-clock BIST scheme has the advantages of very short test application time and small test data volume. However, conventionally this scheme needs an extra parallel response monitor for response analysis that may lead to large area overhead. This paper presents a new test-per-clock BIST method that can perform both pattern generation and response compression concurrently in the same LFSR-based design so as to reduce the area overhead. Furthermore, some internal nets are employed in two ways during test application to help reduce test time and test data volume: 1) as the observation points to enhance fault detectability and 2) as the test data provider for reseeding the LFSR. These two ways lead to the benefits that all required patterns can be generated on chip and at-speed testing can be carried out without using any external or internal storage device. Experimental results show that the presented method can achieve 100% fault coverage in very short time for large ISCAS (IWLS) benchmark circuits using 0.09% (0.03%) of internal nets with 9.29% (8.26%) extra area overhead respectively. When compared with a conventional scan-based design, the area overhead is small considering the features of test-per-clock and no requirement of data storage or expensive test equipment.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 2016 五月 31
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 2016 四月 252016 四月 27

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家/地區Taiwan
城市Hsinchu
期間16-04-2516-04-27

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 儀器

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